Samsung has just announced the introduction of two new advanced process nodes: SF2Z (2nm) and SF4U (4nm). The lower the nm number of the process node, the better. Samsung’s new 2nm process node, SF2Z, incorporates a backside power delivery network (BSPDN), which enhances power, performance, and area (PPA) and also reduces voltage drop. PPA are the three variables used in deciding how to optimize semiconductor designs. On the other hand, the 4nm node, SF4U, achieves PPA improvements through optical shrink technology, enabling existing die designs to be scaled down without significant architectural changes. These advanced process nodes are expected to enter mass production in 2025 (4nm) and 2027 (2nm), primarily targeting HPC and AI chips.
I believe that the technology will transfer onto smartphone chips – this could very well be the next chapter in the Samsung-Apple rivalry, where each side tries to deliver cutting-edge technology and attract more customers.
Nanometer (nm) nodes refer to the size of the transistors on a chip, with smaller numbers indicating smaller transistors. Smaller transistors are more efficient, allowing more of them to fit on a chip, which in turn enhances the chip’s performance and reduces power consumption. For example, older chips with 10nm transistors are like drawing with a thick marker, fitting fewer transistors and resulting in less efficient and slower smartphones. In contrast, current 5nm, 4nm and 3nm chips, akin to using a fine-tip pen, fit more transistors, leading to better performance and longer battery life. Future 2nm chips, comparable to using a super fine mechanical pencil, will further improve efficiency and power, making smartphones even faster and more energy-efficient.